In many electronic applications it would be an advantage if the instantaneous phase angle of an A.C. electrical signal was available directly in a digital representation. The digital representation is especially useful if subsequent numerical processing of the signal is to take place. Today, several special chips for digital signal processing are available, and processing the signal digitally provides many advantages over ordinary analog signal processing. For example, digital filters do not suffer from the component value spread associated with analog filters, and a designer can implement more complex algorithms when using digital techniques.
One use of the digital phase representation of a signal would be to demodulate digitally a phase modulated radio signal. If all subsequent filtering of the signal were also to be done digitally, such a technique would obviate the need for analog components in the radio receiver, except for the digital-to-analog converter and the radio frequency portions. It would also be possible to demodulate a frequency modulated signal, since the frequency is the derivative of the phase. The frequency, therefore, can be calculated by differentiating the phase samples using a simple digital subtraction.
Since the phase of a constant frequency signal forms a continuously incrementing ramp, the true phase representation of the signal occupies an infinite number of binary bits. The solution to this problem is to represent the phase as modulo 2Pi. If, for example, an eight bit binary word is chosen to represent the phase, then a circular phase angle in the range 0 . . . 2Pi can be mapped to match exactly the circular domain, or Galois field, of a binary word in the range 0 . . . 256. This mapping of one circular domain onto the other greatly simplifies the numerical processing.
There are several known methods of digitizing the phase of an analog A.C. input signal. One method is to use an analog phase comparator which is fed with an input signal together with a reference signal. The output of the comparator is then fed to an analog-to-digital converter that provides the desired digital representation. This method requires (1) the phase comparator to be very linear and (2) the output phase-to-voltage conversion factor from the comparator to match exactly the voltage to code conversion factor of the analog-to-digital convertor. If these two requirements are not satisfied, then an error in the mapping of one circular domain onto the other will occur. This error can be amplified in the numerical processing of the signal, for example, when differentiating the phase in order to demodulate a frequency modulated signal. Another drawback of this method is that the method cannot be implemented using only digital logic components.
Another method, that is very closely related to the method described above, is to use a frequency discriminator with an analog-to-digital converter instead of the phase comparator, and then the phase is re-integrated from the frequency samples. The phase obtained with this method will, of course, only be an estimate of the actual phase.
Still another method includes quadrature phase detectors, which is often referred to as the I,Q method. There are a limited number of phase comparators that can operate correctly with a noisy signal in the entire range 0 to 2Pi. It is particularly difficult for the comparator when the phase is in the area of 2Pi or 0, where the circular phase wraps around. The I,Q method uses two phase comparators, instead of one, and each comparator is fed with a reference signal that is offset by 90 degrees with respect to the other. At least one of the two comparators will operate well away from the discontinuity.
A method often used in commercial frequency counters is the digital counter-discriminator. The number of input signal cycles that occur during a fixed time interval is counted, and the count is used as a measurement of the frequency. In order to obtain an acceptable accuracy in the frequency, the time interval has to be substantially longer than the input signal cycle period. For example if 1% accuracy is required, then the measurement period must be at least 100 times the signal period. Accordingly, a measurement obtained using this method is an average measurement. The frequency samples then have to be reintegrated, if a phase output is desired.
Another method that is commonly used in frequency counters is to measure the period of the input signal. The frequency can then be calculated as the reciprocal of the period time. The time measurement can be implemented very easily using a counter that is reset on the first input signal edge and then read on the next. In order to obtain a high resolution measurement, the clock frequency of the counter has to be substantially higher than the input signal frequency. Another drawback of this method is that the signal is sampled on the edge of the input signal, i.e., the so-called natural sampling. It is, however, often preferable to sample and digitize a signal at regular intervals that are independent of a noisy or varying signal.
A better method of digitizing the phase is described in copending U.S. Pat. No. 5,084,669, entitled "Direct Phase Digitization", by Paul Dent, and assigned to the assignee of the present application. This improved method reads the position of a rotating reference phase vector on the edges of the input signal and uses the vector angle as the phase sample. FIG. 1 shows a simplified block diagram of the phase digitizing device 10 of the copending application. The main blocks of the digitizer 10 are the counter 11, the latches 12 and 13, and the trigger circuit 14. Assume for the present that a reference clock frequency is available which is an integer multiple, preferably binary, of the input signal frequency. The reference clock is applied to the digital counter 11 which divides by the predetermined multiple so that a divider count cycle repeats at the same rate as the expected input frequency. The state of the counter 11 can then be thought of as a phase vector angle that turn exactly one revolution for every unmodulated input signal period. An output value is produced by recording the state of the counter 11, the vector angle, on zero-crossing events of the input signal. In contrast to the other methods described, the counter 11 is never reset and continues to increment between measurements. The recording of the counter state is caused by a trigger signal which is a function of two events. Firstly, the trigger circuit 14 must be armed by receipt of a sampling pulse which indicates that it is desired to make a measurement. Secondly, the trigger circuit 14 fires on the next occurrence of a input signal zero-crossing. The pulse that the trigger circuit 14 generates when it fires causes the state of the counter 11 to be transferred to the intermediate holding register or latch 12. The result is held in the latch 12 until the next sampling pulse is applied to the trigger circuit 14. The result is then transferred to the output latch 1 before it is replaced by the next measurement. Measurements, therefore, occur at the output register or latch 13 with a one sample delay and at a regular rate determined by the externally applied sampling signal. An extra bit of precision may be obtained by extending the holding register 12 by one bit and also recording whether the reference clock signal at the trigger firing was on a positive or negative half cycle.
Since the input signal edge which latches the counter state can occur at any time relative to the reference clock edge, it is desirable that the counter 11 be of the Gray code type or some other suitable type. In a Gray code counter only one bit changes on adjacent clock cycles, thus avoiding the danger of erroneous results due to several bits changing at slightly different times. If a Gray code counter is used, it may be convenient to insert a Gray code to binary converter between the holding register 12 and the output register 13.
If the expected input signal frequency is exactly equal to the counter divider repetition cycle rate, the zero crossings will always occur at the same counter state, which depends on the arbitrary phase of the signal relative to the master clock. For example, assuming that the counter 11 divides by 64, the sequence of numbers produced may be 29, 29, 29 . . . If the expected signal frequency is lower than the counter repetition rate, the zero crossings will occur on progressively later counter states. For example, 60, 62, 0, 1, 3 . . . , the counter wrapping around at 64. The exact expected number of increments between the samples in this example is 64 times the frequency offset times the sample period. For example, if the expected signal frequency is 1000 Hz lower than the counter repetition rate, and the sampling frequency is 256 Hz, then the expected increment between samples will be 64*1000/256 modulo 64=3 29/32nds.
The above-described example has been chosen such that the expected increment is not an integer in order to illustrate that the cumulative increment can still be predicted by extending the precision to the right of an imagined binary point to represent the fractional part. In the above-described example, a binary accumulator (not shown) with five bits to the right of the decimal point to represent numbers in steps of 1/32nd. The accumulator would then be incremented after every sample by the digital value 000011.11101 representing 3 29/32.
The value in the binary accumulator represents the systematic phase offset a signal at exactly the specified nominal frequency would have accumulated up to this point due to frequency offset from the reference counter's 11 repetition rate. The increment to the binary accumulator represents the extra phase rotation added every time due to the systematic frequency offset integrated over a sampling interval. By subtracting the accumulated phase offset from the phase measurement before transferring it to the output register 13, it is corrected for both the systematic frequency error and the non-commensurate sampling rate. It, therefore, becomes possible to choose the signal center frequency, the reference frequency and the sampling rate independently of each other, within reasonable practical limits.
The main drawback with the above-described reference vector method of phase digitization relates to the correction of the measurement. For certain combinations of input, reference and sampling signal frequencies the correction may generate a tone that will interfere with the phase information. For example, if a 2 MHz reference clock is fed to a modulo 64 counter, the nominal signal frequency is 34 kHz and the sample frequency is 16 kHz. The correction increment, therefore, would exactly be 64*(2 Mhz/64-34 kHz)/16 kHz=-11.
Consecutive output samples will then be corrected by adding 11, 22, 33, 44, 55, 2, 12 . . . to the measurements. This correction completely compensates for the average frequency offset, however, every measurement is made on the zero crossing of the input signal not on the sampling pulse. There is exactly 34 kHz/16 kHz=2 1/8 signal periods for every sample pulse period. This means that seven times out of eight the measurements are taken every second signal zero crossing, but the eighth measurement is taken after three zero crossings. Since the actual time between measurements is shorter than the sample period for the first seven measurements, these samples will be overcompensated by the correction, thereby creating a ramp. The eighth measurement is taken after a time that is longer than the sample period and will, therefore, be under compensated. The result will be a 16 kHz/8=2 kHz sawtooth waveform superimposed on the phase signal. The peak to peak amplitude of the sawtooth will be 7/8*11*16 kHz/34 kHz=4.53 least significant bits. This may not be acceptable in many applications. The peak to peak amplitude of the sawtooth may, however, be reduced to half by measuring the phase on both the positive and negative zero crossings of the signal. This will also double the sawtooth frequency, but the output sample will then have to be corrected by 180 degrees, when latched on a negative zero crossing. One easy way to shift the phase 180 degrees is to invert the most significant bit of the output sample, i.e., adding -Pi in twos complement form.
Another problem of the above-described reference vector method is the asynchronous latching of the phase which demands the use of a Gray coded reference counter 11. If the reference clock state is to be used to obtain an extra bit of precision the trigger circuit 14 will have to be implemented asynchronously, unless of course a higher clock frequency than the reference clock is available. Asynchronous designs can be a nuisance.
Accordingly, there is a need for an improved phase digitizer which can provide a digital representation of an analog signal without the drawbacks associated with the above-described devices.